The ARM Cortex™-A15 MPCore™ processor delivers unprecedented processing capability, combined with low power consumption to enable compelling products in a wide range of new and existing ARM markets ranging from mobile computing, high-end digital home, servers and wireless infrastructure.
The Cortex-A15 MPCore processor is the latest member of the Cortex-A series of processors, ensuring full application compatibility with all of the other highly acclaimed Cortex-A processors. This enables immediate access to an established developer and software ecosystem including Android™, Adobe® Flash® Player, Java Platform Standard Edition (Java SE), JavaFX, Linux, Microsoft Windows Embedded, Symbian and Ubuntu, along with more than 700 ARM Connected Community™ members providing applications software, hardware and software development tools, middleware and SoC design services.
The Cortex-A15 processor has an out-of-order superscalar pipeline with a tightly-coupled low-latency level-2 cache which can be up to 4MB in size. Additional improvements in floating point and NEON™ media performance result in devices that deliver the next-generation user experience for consumers as well as high-performance computation for web infrastructure applications.
It is expected that mobile configurations of the Cortex-A15 MPCore processor will deliver over five times the performance of today’s advanced smartphones. In advanced infrastructure applications, the Cortex-A15 running at up to 2.5GHz will enable highly scalable solutions within constantly shrinking energy, thermal and cost budgets.
The Cortex-A15 processor is built around the ARMv7A architecture and ensures full software compatibility with the rest of the highly acclaimed Cortex-A processors. This enables immediate access to an established developer and software ecosystem including Android™, Adobe® Flash® Player, Java Platform Standard Edition (Java SE), JavaFX, Linux, Microsoft Windows Embedded, Symbian and Ubuntu, along with more than 1000 ARM Connected Community™ members providing applications software, hardware and software development tools, middleware and SoC design services.
To achieve the very best performance, the Cortex-A15 processor has a multi-issue, out-of-order superscalar pipeline with a tightly-coupled low-latency, ECC-protected,level-2 cache which can be up to 4MB in size. Now able to address 1TB of physical memory, the Cortex-A15 processor is able to meet the needs of server and networking applications.
Extending ARM’s leadership in the mobile space, the Cortex-A15 processor will deliver twice the performance of today’s smartphones based on the Cortex-A9 processor. This is a level of performance once only seen in laptops now in a mobile thermal and power envelope. This also represents over five times the performance of smartphones based on the Cortex-A8 processor.
World-class performance leadership is brought to a new level with unique-to-ARM technology called “big.LITTLE”. A big.LITTLE configuration pairs a high-performance core like the Cortex-A15 MPCore processor with a power-optimized companion core, like the Cortex-A7 processor using a fabric like Corelink™ CCI-400. This paring solves the contradictory challenges of increasing performance while increasing battery life, by ensuring that the right processor core is assigned to the right task. In advanced infrastructure applications, the Cortex-A15 processor running at up to 2.5GHz will enable highly scalable solutions within constantly shrinking energy, thermal and cost budgets. Paired with advanced fabric technology like Corelink CCN-504, the Cortex-A15 MPCore processor is the engine that powers not just smart phones but also the infrastructure that smart phones rely on. From servers to networking to your high end digital home entertainment systems, the Cortex-A15 processor is the right solution for a very diverse set of solutions.
- Advanced Smartphones
- Mobile Computing
- High-end Digital Home Entertainment
- Wireless Infrastructure
- Low-power Servers
The growing complexity of the Web2.0 centric devices is creating the requirement for devices to support multiple software personalities and combine disparate functionality. For this reason the Cortex-A15 MPCore processor introduces new technology from ARM that enables efficient handling of the complex software environments including full hardware virtualization, Large Physical Address Extensions (LPAE) addressing up to 1TB of memory as well as error correction capability for fault-tolerance and soft-fault recovery.
The Cortex-A15 MPCore processor is the first ARM processor to incorporate highly efficient hardware support for data management and arbitration, enabling multiple software environments and their applications to simultaneously access the system capabilities. This enables the realization of devices that are robust, with virtual environments that are isolated from each other.
The ARM philosophy is that one size does not fit all. Mobile performance has two opposite targets – responsiveness / frame rate for gaming and web surfing coupled with maximizing the battery life so that a truly un-tethered experience is reality. Mobile configurations of the Cortex-A15 MPCore processor, which will include the Cortex-A7 MPCore processor and CCI-400 to tie them together, are expected to deliver over twice the performance of today’s top-of-the-line smartphones and over 4 times the aggregate performance of ARM processor-based infrastructure platforms, combined with ARM's signature low power consumption.
To answer the call to meet both targets simultaneously, ARM has answered with big.LITTLE technology. By offering a ‘right core for the right task’ solution, ARM can offer a major technology inflection point. ARM’s big.LITTLE technology assigns background and light tasks to the “LITTLE” core and the primary larger tasks to the “big” core. Not only does this allow the larger core to operate more efficiently because it is not trying to context switch all the time to cover the light threads, the consumer wins with greatly increased battery life while realizing the top-end performance that can be greater than what a Cortex-A15 MPCore processor can do by itself. Listed below are examples of expected application-specific implementations:
|Smartphone and Mobile Computing|
|Digital Home Entertainment|
|Home and Web 2.0 Servers|
1.5GHz – 2.5 GHz quad-core, octal-core or larger configurations using CCI-400 or CCN-504
1.5GHz – 2.5 GHz quad-core Cortex-A15 MPCore paired with 1.0GHz – 1.5GHz Cortex-A7 MPCore using CCI-400
ARMv7 Memory Management Unit
|Debug & Trace||CoreSight™ SoC|
|Cortex-A15 MPCore Key Features|
|Thumb-2 Technology||Delivers the peak performance of traditional ARM code while also providing up to a 30% reduction in memory required to store instructions|
|TrustZone Technology||Ensures reliable implementation of security applications ranging from digital rights management to electronic payment Broad support from technology and industry Partners|
|NEON||NEON technology can accelerate multimedia and signal processing algorithms such as video encode/decode, 2D/3D graphics, gaming, audio and speech processing, image processing, telephony, and sound synthesis|
|DSP & SIMD Extensions||Increase the DSP processing capability of ARM solutions in high-performance applications, while offering the low power consumption required by portable, battery-powered devices. The DSP extensions are optimized for a broad range of software applications including servo motor control, Voice over IP (VOIP) and video & audio codecs.|
|Floating Point||Hardware support for floating point operations in half-, single- and double-precision floating point arithmetic. The floating-point capabilities of the Cortex-A15 processor offer increased performance for floating point arithmetic used in next generation of consumer products such as Internet appliances, set-top boxes, and home gateways.|
|Hardware Virtualization||The Cortex-A15 MPCore processor is the first ARM processor to incorporate highly efficient hardware support for data management and arbitration, whereby multiple software environments and their applications are able to access the system capabilities simultaneously. This enables the realization of devices that are robust, with virtual environments that are well isolated from each other.|
|Large Physical Address Extensions (LPAE)||The introduction of Large Physical Address Extensions (LPAE) enables the processor to access up to 1TB of memory.|
|Optimized Level 1 Caches||Performance and power optimized L1 caches combine minimal access latency techniques to maximize performance and minimize power consumption. Caches are 32KB for instruction and 32KB for data. Also providing the option for cache coherence for enhanced inter-processor communication or support of rich SMP capable OS for simplified multicore software development|
|Integrated, Configurable Size Level 2 Cache Controller||Providing low latency and high bandwidth access to up to 4 MB of cached memory in high frequency designs, or design needing to reduce the power consumption associated with off chip memory access|
|Reliability and Soft Fault Recovery||All RAMs within the Cortex-A15 processor including L1 and L2 caches are protected by parity and ECC error correction. This mechanism can correct single-bit errors, detect double-bit errors and log errors. The ECC support does not penalize the common case (no errors)|
AMBA® 4 CoreLink CCI-400 Cache Coherent
Interconnect CoreLink CCN-504 Cache Coherent Network
CoreLink CCI-400 provides AMBA 4 AXI™ Coherency Extensions (ACE) compliant ports for full coherency between multiple Cortex-A15 MPCore processors, better utilizing caches and simplifying software development. This IP is essential for high bandwidth applications including gaming, servers and networking that require clusters of coherent single and multicore processors. Combined with the ARM CoreLink™ network interconnect and memory controller IP, the CCI increases system performance and power efficiency.
CoreLink CCN-504 extends the capabilities of your SoC. Up to 16 cores on the same silicon die are possible with this fully-coherent, high-performance many-core solution. With up to 1TB/s of system bandwidth, and support for large L3 caches, SoC designers can address the needs of networking, server, and other enterprise-class devices.
|Cortex-A15 NEON Media Processing Engine (MPE)||The Cortex-A15 MPE provides an engine that offers both the performance and functionality of the Cortex-A15 Floating-Point Unit plus an implementation of the NEON Advanced SIMD instruction set for further acceleration of media and signal processing functions. The MPE extends the Cortex-A15 processor's floating-point unit (FPU) to provide a quad-MAC and additional 64-bit and 128-bit register set supporting a rich set of SIMD operations over 8, 16 and 32-bit integer and 32-bit Floating-Point data quantities every cycle.|
|Cortex-A15 Floating-Point Unit (FPU)||The FPU provides high-performance single, and double precision Floating-Point instructions compatible with the ARM VFPv4 architecture that is software compatible with previous generations of ARM Floating-Point coprocessor.|
|Advanced MultiCore Features|
|The processor also utilizes the widely established ARM MPCore multicore technology, enabling performance scalability and control over power consumption to exceed the performance of today's comparable high-performance devices while remaining within tight mobile power constraints. Multicore processing provides the ability for any of the four component processors to shut down when not in use, for instance when the device is in standby mode, to save power. When higher performance is required, every processor is in use to meet the demand while still sharing the workload to keep power consumption as low as possible.|
|Snoop Control Unit||The SCU is responsible for managing the interconnect, arbitration, communication, cache-2-cache and system memory transfers, cache coherence and other capabilities for the processor. The Cortex-A15 MPCore processor also exposes these capabilities to other system accelerators and non-cached DMA driven peripherals to increase performance and reduce system wide power consumption. This system coherence also reduces software complexity involved maintaining software coherence within each OS driver.|
|Accelerator Coherence Port||This AMBA 4 AXI™-compatible slave interface on the SCU provides an interconnect point for masters that are better interfaced directly with the Cortex-A15 processor. This interface supports all standard read and write transactions without additional coherence requirements. However, any read transactions to a coherent region of memory will interact with the SCU to test whether the information is already stored in the L1 caches. The SCU will enforce write coherence before the write is forwarded to the memory system and may allocate into the L2 cache, removing the power and performance impact of writing directly to off chip memory|
|Generic Interrupt Controller||Implementing the standardized and architected interrupt controller, the GIC provides a rich and flexible approach to inter-processor communication and the routing and prioritization of system interrupts.Supporting up to 224 independent interrupts, under software control, each interrupt can be distributed across CPU, hardware prioritized, and routed between the operating system and TrustZone software management layer. This routing flexibility and the support for virtualization of interrupts into the operating system, provides one of the key features required to enhance the capabilities of a solution utilizing a hypervisor.|
The Cortex-A15 MPCore processor incorporates a broad range of ARM technology including System IP, Physical IP, and development tools that also provide support. A broad range of SoC and software design solutions, tools and services from the ARM Connected Community™ compliment this technology. That provides ARM Partners with a smooth path through the development, verification and production of full function, compelling devices while significantly reducing time-to-market.
The ARM™ interconnect and memory controller IP addresses the critical challenge of efficiently moving and storing data between multiple Cortex-A15 MPCore processors, high performance media processors and dynamic memories to optimize the system performance and power consumption of the SoC. The CoreLink system IP enables SoC designers to maximize the utilization of system memory bandwidth and reduce static and dynamic latencies. While the ARM CoreSight technology provides complete on-chip debug and correlated, real-time trace visibility for all cores of the Cortex-A15 MPCore processor, reducing risk and speeding development of high quality multiprocessing software.
The new AMBA® 4 Cache Coherent Interconnect (CCI) provides Optimum system bandwidth and latency. The CCI provides AMBA 4 AXI™ Coherency Extensions (ACE) compliant ports for full coherency between multiple Cortex-A15 MPCore processors, better utilizing caches and simplifying software development. This feature is essential for high bandwidth applications including gaming, servers and networking that require clusters of coherent single and multicore processors. Combined with the ARM CoreLink network interconnect and memory controller IP, the CCI increases system performance and power efficiency.
ARM Physical IP Platforms deliver process optimized IP, for best-in-class implementations of the Cortex-A15 processor at 40nm and below. A set of high performance Processor Optimization Packs (POPs) containing advanced ARM Physical IP for 28nm technologies supports the Cortex-A15, to enabling rapid development of leadership physical implementations. ARM is also working early to assure a roadmap to 20nm optimizations.
Optimization packs support ARM's strategy of offering specifically targeted Physical IP to enable Partners to achieve tuned implementations of ARM cores. ARM is uniquely able to design the optimization packs in parallel with the Cortex-A15 MPCore processor architecture, enabling the processor and physical IP combination to deliver workstation class performance in a mobile power envelope while facilitating rapid time-to-market.
The ARM Development Suite 5 (DS-5™) tool suite fully supports all ARM processors as well as a wide range of third party tools, operating systems and EDA flows. ARM DS-5 software development tools are unique in their ability to provide solutions that take full advantage of the complete ARM technology portfolio.
The ARM DS-5 provides a complete range of software tools to create, debug and optimize systems based on the Cortex-A15 MPCore processor. It incorporates the DS-5 Debugger, whose powerful and intuitive graphical environment enables fast debugging of bare metal, Linux and Android native applications. In addition, its new ARM Streamline™ Performance Analyzer simplifies the identification of hot spots in software and load balancing between cores. The ARM Compiler, which already includes specific optimizations for the Cortex-A15 MPCore processor, enables early software development before silicon availability and an ARM Versatile™ Reference Virtual Platform built on ARM Fast Models technology.
Media Processors The Mali™ family of products combine to provide the complete graphics stack for all embedded graphics needs, enabling device manufacturers and content developers to deliver the highest quality, cutting edge graphics solutions across the broadest range of consumer devices.
ARM training courses and Active Assist on-site system-design advisory services enable licensees to integrate efficiently the Cortex-A15 MPCore processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.