The combination of high-efficiency signal processing functionality with the low-power, low cost and ease-of-use benefits of the Cortex-M family of processors is designed to satisfy the emerging category of flexible solutions specifically targeting the motor control, automotive, power management, embedded audio and industrial automation markets.
Award-winning energy efficient digital signal control
The Cortex-M4 offers unparalleled capability to integrate 32-bit control with leading digital signal processing techniques for markets that require very high levels of energy efficiency.
The Cortex-M4 makes signal processing algorithm development easy through an excellent ecosystem of software tools and the Cortex Microcontroller Software Interface Standard (CMSIS) .
ARM Cortex-M4 Specification
|ARM Cortex-M4 Features|
|ISA Support||Thumb® / Thumb-2|
|DSP Extensions||Single cycle 16,32-bit MAC
Single cycle dual 16-bit MAC
8,16-bit SIMD arithmetic
Hardware Divide (2-12 Cycles)
|Floating Point Unit||Single precision floating point unit
IEEE 754 compliant
|Pipeline||3-stage + branch speculation|
|Performance Efficiency||3.40 CoreMark/MHz* - 1.25 to 1.52 DMIPS/MHz**|
|Memory Protection||Optional 8 region MPU with sub regions and background region|
|Interrupts||Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts|
|Interrupt Priority Levels||8 to 256 priority levels|
|Wake-up Interrupt Controller||Up to 240 Wake-up Interrupts|
|Sleep Modes||Integrated WFI and WFE Instructions and Sleep On Exit capability.
Sleep & Deep Sleep Signals.
Optional Retention Mode with ARM Power Management Kit
|Bit Manipulation||Integrated Instructions & Bit Banding|
|Debug||Optional JTAG & Serial-Wire Debug Ports. Up to 8 Breakpoints and 4 Watchpoints.|
|Trace||Optional Instruction Trace (ETM), Data Trace (DWT), and Instrumentation Trace (ITM)|
** The lower result is with inlining turned off (as per dhrystone recommendations), the higher result is with inlining turned on (as reported for other processor architectures). Dhrystone v2.1.
|ARM Cortex-M4 Implementation Data***|
7-track, typical 1.8v, 25C)
7-track, typical 1.2v, 25C)
9-track, typical 0.9v, 25C)
|Dynamic Power||157 µW/MHz||33 µW/MHz||8 µW/MHz|
|Floorplanned Area||0.56 mm2||0.17 mm2||0.04 mm2|
*** Base usable configuration includes DSP extensions, 1 IRQ + NMI, excludes ETM, MPU, FPU and debug
ARM Cortex-M technologies
|RISC processor core||Thumb-2® technology|
|Tools and RTOS support||CoreSight debug and trace|
|Low power modes||Nested Vectored Interrupt Controller (NVIC)|
The ARM Cortex Microcontroller Software Interface Standard (CMSIS) is a vendor-independent hardware abstraction layer for the Cortex-M processor series.The CMSIS enables consistent and simple software interfaces to the processor for interface peripherals, real-time operating systems, and middleware, simplifying software re-use. With a reduced learning curve for new microcontroller developers, CMSIS shortens the time to market for new products.
In-depth: Nested Vectored Interrupt Controller (NVIC)
The NVIC is an integral part of all Cortex-M processors and provides the processors' outstanding interrupt handling abilities. In the Cortex-M0, Cortex-M0+ and Cortex-M1 processors, the NVIC support up to 32 interrupts (IRQ), a Non-Maskable Interrupt (NMI) and various system exceptions. The Cortex-M3 and Cortex-M4 processors extend the VIC to support up to 240 IRQs, 1 NMI and further system exceptions.
Most of the NVIC settings are programmable. The configuration registers are part of the memory map and can be accessed as C pointers. The CMSIS library also provided various helper functions to make interrupt control easier.
Inside the NVIC, each interrupt source is assigned an interrupt priority. A few of the system exceptions like such as NMI haves a fixed priority level, and others hashave programmable priority levels. By assigning different priorities to each interrupt, the NVIC can support Nested Interrupts automatically without any software intervention.
The architecture provides 8-bits of priority level settings for each programmable interrupt or exception. To reduce gate count, only parts of these registers are implemented. In the Cortex-M0, Cortex-M0+ and Cortex-M1 processors (ARMv6-M architecture), 4 programmable levels are provided. In the Cortex-M3 and Cortex-M4 processors (ARMv7-M architecture), the designs allow from 8 priority levels to 256 levels.
To make the Cortex-M processors easier to use, the Cortex-M processor uses a stack based exception model. When an exception takes place a number of registers are pushed on to the stack. These registers are restored to their original values when the exception handler completes. This allows the exception handlers to be written as normal C functions, and also reduce the hidden software overhead ofin interrupt processing.
In addition, the Cortex-M processors use a vector table that contains the address of the function to be executed for eacha particular interrupt handler. On accepting an interrupt, the processor fetches the address from the vector table. Again, this avoids software overhead and reduces interrupt latency.
Various optimization techniques are also used in the Cortex-M processor implementationss to make interrupt processing more efficiency and make the system more responsive:
Tail chaining – If another exception is pending when an ISR exits, the processor does not restore all saved registers from the stack and instead moves on to the next ISR. This reduces the latency when switching from one exception handler to another.
Stack pop pre-emption – If another exception occurs during the unstacking process of an exception, the processor abandons the stack Pop and services the new interrupt immediately as shown above. By pre-empting and switching to the second interrupt without completing the state restore and save, the NVIC achieves lower latency in a deterministic manner.
Late arrival – If a higher priority interrupt arrives during the stacking of a lower priority interrupt, the processor fetches a new vector address and processes the higher priority interrupt first.
With these optimizations, the interrupt overhead reduces as the interrupt loading increases, allowing high interrupt processing throughput in embedded systems.
System IP components are essential for building complex system on chips and by utilizing System IP components developers can significantly reduce development and validation cycles, saving cost and reducing time to market.
|Description||AMBA Bus||System IP Components|
|AMBA Design Kit (ADK)||AHB||ADK|
|AMBA DMA Controllers||AHB||DMA Controller|
|ARM® Physical IP Platforms deliver process optimized IP, for best-in-class implementations of the Cortex-M4 processor.|
|Standard Cell Logic Libraries||Available in a variety of different architectures ARM Standard Cell Libraries support a wide performance range for all types of designs. Designers can choose between different libraries and optimize their designs for speed, power and/or area|
|Memory Compilers and Registers||A broad array of silicon proven SRAM, Register File and ROM memory compilers for all types of designs ranging from performance critical to cost sensitive and low power applications|
|Interface Libraries||A broad portfolio of silicon-proven Interface IP designed to meet varying system architectures and standards. General Purpose I/O, Specialty I/O, High Speed DDR and Serial Interfaces are optimized to deliver high data throughput performance with low pin counts.|
All ARM processors are supported by the ARM Development Studio 5 (DS-5™) tool suite, as well as a wide range of third party tools, operating system and EDA vendors. ARM DS-5 software development tools are unique in their ability to provide solutions that take full advantage of the complete ARM technology portfolio.
Microcontroller development tools details are available at the Keil website.
|Definitive Guide to the ARM Cortex-M0
A comprehensive guide to programming and implementing the groundbreaking ARM Cortex-M0 processor
|Definitive Guide to the ARM Cortex-M3
A comprehensive guide to programming and implementing the groundbreaking ARM Cortex-M3 processor
Documentation for Cortex-M device users
Software development tools for Cortex-M device users
Find Cortex-M based microcontrollers
Related User Guides and App Notes
Cortex-M0/3/4 Devices Generic User Guides
- Software Development
Instruction Timing Information
- Cortex-M0 Technical Reference Manual (TRM)
- Cortex-M3 Technical Reference Manual (TRM)
- Cortex-M4 Technical Reference Manual (TRM)
Architecture (requires registration)
ARM Application Notes
- AN237 - Migrating from 8051 to Cortex Microcontrollers
- AN234 - Migrating from PIC Microcontrollers to Cortex-M3
- AN179 - Cortex™-M3 Embedded Software Development
Keil Application Notes
- 193: Migrating to MDK-ARM from RVDS
- 197: Serial-Wire Debug and Realtime Trace on STM32 Devices
- 202: MDK-ARM Compiler Optimizations
- 208: Keil uVision and Actel SmartFusion
- 209: Using Cortex-M3 and Cortex-M4 Fault Exceptions
- 220: Memory Configuration on Freescale Kinetis devices
- 221: Using CMSIS-DSP Algorithms with RTX